1. Field of the Invention
Generally, the present disclosure relates to integrated circuits, and, more particularly, to semiconductor elements, such as substrate diodes, of SOI circuits formed in the crystalline material of the substrate.
2. Description of the Related Art
The fabrication of integrated circuits requires a large number of circuit elements, such as transistors and the like, to be formed on a given chip area according to a specified circuit layout. Generally, a plurality of process technologies are currently practiced, wherein, for complex circuitry, such as microprocessors, storage chips, ASICs (application specific ICs) and the like, CMOS technology is currently one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using CMOS technology, millions of complementary transistors, i.e., N-channel transistors and P-channel transistors, are formed above a substrate including a crystalline semiconductor layer. A MOS transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, comprises so-called PN junctions that are formed by an interface of highly doped drain and source regions with an inversely or weakly doped channel region disposed between the drain region and the source region. The conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed above the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on the dopant concentration, the mobility of the charge carriers and, for a given extension of the channel region in the transistor width direction, on the distance between the source and drain regions, which is also referred to as channel length. Hence, in combination with the capability of rapidly creating a conductive channel below the insulating layer upon application of the control voltage to the gate electrode, the conductivity of the channel region substantially determines the performance of the MOS transistors. Thus, the latter aspect makes the reduction of the channel length, and associated therewith the reduction of the channel resistivity, a dominant design criterion for accomplishing an increase in the operating speed of the integrated circuits.
In view of further enhancing performance of transistors, in addition to other advantages, the SOI (semiconductor- or silicon-on-insulator) architecture has continuously been gaining in importance for manufacturing MOS transistors due to their characteristics of a reduced parasitic capacitance of the PN junctions, thereby allowing higher switching speeds compared to bulk transistors. In SOI transistors, the semiconductor region, in which the drain and source regions as well as the channel region are located, also referred to as the body, is dielectrically encapsulated. This configuration provides significant advantages, but also gives rise to a plurality of issues. Contrary to the body of bulk devices, which is electrically connected to the substrate and thus applying a specified potential to the substrate maintains the bodies of bulk transistors at a specified potential, the body of SOI transistors is not connected to a specified reference potential, and, hence, the body's potential may usually float due to accumulating minority charge carriers, unless appropriate counter measures are taken.
A further issue in high performance devices, such as microprocessors and the like, is an efficient device internal temperature management due to the significant heat generation. Due to the reduced heat dissipation capability of SOI devices caused by the buried insulating layer, the corresponding sensing of the momentary temperature in SOI devices is of particular importance.
Typically, for thermal sensing applications, an appropriate diode structure may be used, wherein the corresponding characteristic of the diode may permit information to be obtained on the thermal conditions in the vicinity of the diode structure. The sensitivity and the accuracy of the respective measurement data obtained on the basis of the diode structure may significantly depend on the diode characteristic, i.e., on the diode's current/voltage characteristic, which may depend on temperature and other parameters. For thermal sensing applications, it may, therefore, typically be desirable to provide a substantially “ideal” diode characteristic in order to allow a precise estimation of the temperature conditions within the semiconductor device. In SOI devices, a corresponding diode structure, i.e., the respective PN junction, is frequently formed in the substrate material located below the buried insulating layer, above which is formed the “active” semiconductor layer used for forming therein the transistor elements. Thus, at least some additional process steps may be required, for instance, for etching through the semiconductor layer or a corresponding trench isolation area and through the buried insulating layer in order to expose the crystalline substrate material. On the other hand, the process flow for forming the substrate diode is typically designed so as to exhibit a high degree of compatibility with the process sequence for forming the actual circuit elements, such as the transistor structures, without undue negative effects on the actual circuit elements.
In other cases, other circuit elements may have to be formed in the crystalline substrate material on the basis of appropriately designed PN junctions, while not unduly contributing to overall process complexity. Hence, the circuit elements to be formed in the substrate material may typically be fabricated with a high degree of compatibility with the usual manufacturing sequence for the circuit elements formed in and above the active semiconductor layer formed on the buried insulating material. For instance, typically, the PN junctions of the circuit elements in the crystalline substrate material may be formed on the basis of implantation processes, which are also performed in the active semiconductor layer for forming deep drain and source regions in order to provide an efficient overall manufacturing flow. In this case, an opening is typically formed so as to extend through the buried insulating layer and into the crystalline substrate material prior to performing the corresponding implantation process. Consequently, the dopant species may be introduced into the crystalline substrate material, i.e., into the portion exposed by the opening, so that corresponding PN junctions may be substantially aligned to the sidewalls of the opening, thereby also providing a certain “overlap” due to the nature of the implantation process and any subsequent anneal processes that may typically be required for activating the dopant species in the drain and source regions of the transistors and also to re-crystallize implantation-induced damage. However, during the further processing of the semiconductor device, for instance by performing appropriate wet chemical etch and cleaning processes, the lateral dimension of the opening may be increased due to an interaction with aggressive wet chemical etch chemistries. The resulting material removal from sidewalls of the opening may also have a significant influence on corresponding PN junctions formed in the crystalline substrate material, as will be described in more detail with reference to FIGS. 1a-1c. 
FIG. 1a schematically illustrates a cross-sectional view of a semiconductor device 100 that represents an SOI device. The semiconductor device 100 comprises a substrate 101 which includes, at least in an upper portion thereof, a substantially crystalline substrate material 102, which may be pre-doped in accordance with device requirements. For example, the substrate material 102 may have incorporated therein an appropriate locally restricted concentration of a P-type dopant or an N-type dopant and the like. For example, as illustrated, the crystalline substrate material 102 may comprise an N-well region 102A as may be required for forming circuit elements, such as a substrate diode and the like. Furthermore, a buried silicon dioxide layer 103 is formed on the crystalline substrate material 102, followed by a semiconductor layer 104 that is typically provided in the form of a silicon layer, which, however, may also contain other components, such as germanium, carbon and the like, at least in certain device areas. The semiconductor device 100 comprises a first device region 110 which, in the example shown, may comprise a substrate diode 130 including a PN junction 102P. As previously explained, the substrate diode 130 and, thus, in particular, the PN junction 102P may be used as a temperature monitor for evaluating the temperature of the semiconductor device 100 in a locally resolved manner. Consequently, the electronic characteristics of the PN junction 102P may have a significant influence on the accuracy of a corresponding temperature signal obtained on the basis of the substrate diode 130. The PN junction 102P may be defined by a highly P-doped region 132 embedded in the lightly N-doped well region 102A. Moreover, a highly N-doped region 131 may be provided and may act as a contact area for a cathode of the substrate diode 130. In the manufacturing stage shown in FIG. 1a, openings 103A, 103B may be formed in the buried insulating layer 103 and in the semiconductor layer 104 or a corresponding isolation region 105 provided in the layer 104 so as to laterally delineate the first and second device regions 110, 120.
On the other hand, in the device region 120, one or more transistors 140 may be formed in and above the semiconductor layer 104 in accordance with overall device requirements. In the example shown, a planar transistor configuration is illustrated and comprises a gate electrode structure 141 that may comprise an electrode material 141A, such as a polysilicon material and the like, in combination with a gate dielectric material 141B that separates the electrode material 141A from a channel region 143 positioned in the semiconductor layer 104 laterally between drain and source regions 142. Furthermore, the gate electrode structure 141 may comprise a spacer structure 141C, which may have any appropriate configuration so as to act as an implantation mask during an implantation sequence 106 for introducing the dopant species of the drain and source regions 142.
Typically, the semiconductor device 100 as illustrated in FIG. 1a may be formed on the basis of the following processes. The substrate 101 may be provided so as to include the buried oxide layer 103 formed on the crystalline substrate material 102, while the semiconductor layer 104 is formed on the buried insulating layer 103, which may be accomplished on the basis of well-established wafer bond techniques, sophisticated implantation and oxidation processes and the like. Thereafter, the isolation structure 105 in the form of a shallow trench isolation may be formed by using well-established lithography, etch, deposition and planarization techniques in order to obtain isolation trenches filled with an appropriate dielectric material, such as silicon dioxide. Prior to or after forming the isolation structure 105, the basic dopant concentration of the N-well 102A may be defined, for instance by ion implantation. Next, appropriate materials for the gate electrode structure 141 of the transistor 140 may be provided, for instance, by advanced oxidation and/or deposition techniques for providing the gate dielectric material 141B, followed by the deposition of the gate electrode material 141A, for instance in the form of polysilicon and the like. On the basis of sophisticated lithography and etch techniques, these materials are patterned so as to obtain the gate electrode structure 141. Thereafter, appropriate implantation processes are performed in order to introduce a desired dopant concentration adjacent to the gate electrode structure 141, possibly on the basis of any offset spacer elements (not shown). Subsequently, the sidewall spacer structure 141C is formed by well-established techniques, i.e., by depositing an etch stop material (not shown), such as silicon dioxide followed by the deposition of a silicon nitride material, which is then etched by anisotropic techniques. It should be appreciated that the spacer structure 141C may include two or more individual spacer elements if a corresponding complex dopant profile is required for the drain and source regions 142. According to a well-established process strategy, prior to incorporating the final dopant concentration of the drain and source regions 142, the openings 103A, 103B are formed, which may be accomplished by appropriately covering the second device region 120 by an etch mask, which also defines the desired lateral size and position of the openings 103A, 103B in the first device region 110. Thereafter, an anisotropic etch process is performed, for instance for etching through the semiconductor layer 104 or the isolation structure 105 thereof and etching through the buried insulating layer 103 in order to expose portions of the N-well 102A that correspond to the regions 131, 132, respectively. After the etch process for forming the openings 103A, 103B, the etch mask is removed by any appropriate removal process. It should be appreciated that the etch mask may be provided in the form of a hard mask material in combination with resist materials, depending on the overall process strategy. For instance, polysilicon material may be efficiently used as a hard mask material, which may then be removed on the basis of any appropriate etch technique while still covering the second device region 120, for instance on the basis of a resist mask. Thereafter, the further processing may be continued by performing a sequence of implantation processes. In the example shown, it may be assumed that the transistor 140 represents a P-channel transistor in which the drain and source regions 142 may be formed on the basis of a P-type dopant material during the implantation process 106, in which at the same time the P-type region 132 may be formed in the N-well 102A. For this purpose, an implantation mask 107, such as a resist mask and the like, is provided so as to expose the transistor 140 and the opening 103A while covering the opening 103B. Furthermore, in the example shown, a corresponding implantation process may have been performed prior to the process 106 by using an appropriate mask for covering the opening 103A and the transistor 140 while exposing any N-channel transistors (not shown) and the opening 103B, which may thus be used as an implantation mask for forming the N-doped region 131 together with drain and source regions of the exposed N-channel transistors. In other cases, the N-doped region 131 and corresponding drain and source regions of N-channel transistors may be formed after the implantation process 106.
Consequently, the dopant concentration of the region 132 substantially corresponds to the dopant concentration of deep drain and source areas of the region 142 of the transistor 140. For this reason, the characteristics of the PN junction 102P may be determined by process conditions required for obtaining a desired dopant profile for the drain and source regions 142 of the transistor 140. Thereafter, typically, appropriately designed anneal processes are performed in order to activate the dopant species and also re-crystallize implantation-induced damage. Due to the nature of the implantation process 106 and due to the subsequent anneal processes, the PN junction 102P may be driven “outwardly,” as indicated by the dashed line 102F, so that a certain degree of overlap between the layer 103 and the highly doped region 132 is obtained depending on the process parameters of the previously performed process sequence. Hence, the magnitude of the resulting overlap may be substantially determined by the process parameters, which are typically selected so as to obtain superior characteristics of the drain and source regions 142, in particular when extremely scaled transistor devices are considered. For example, in sophisticated planar transistor configurations, a gate length, i.e., in FIG. 1a, the horizontal extension of the electrode material 141A, may be approximately 50 nm and less, thereby also requiring precisely defined characteristics of the drain and source regions 142. For example, a pronounced dopant diffusion in the drain and source regions 142 may typically be avoided in order to obtain a desired steep dopant gradient for the drain and source regions 142.
Thereafter, the further processing is continued by performing further manufacturing steps as are required for completing the basic transistor configuration in the device region 120. In particular, one or more sophisticated wet chemical cleaning or etch processes have to be performed in order to prepare exposed surface portions of the device 100 for forming a metal silicide in the drain and source regions 142 and possibly in the gate electrode structure 141, thereby also forming corresponding metal silicide areas in the regions 131, 132. Typically, the provision of a metal silicide may be required for reducing the overall contact resistivity of the transistor 140 and also of the diode 130.
FIG. 1b schematically illustrates the semiconductor device 100 during a wet chemical etch process 108 which is typically designed to remove oxide from exposed silicon surfaces in order to provide enhanced surface conditions during the subsequent silicidation process. Consequently, during the wet chemical process 108, exposed sidewall portions 103S of at least the buried insulating layer 103 in the openings 103A, 103B may also be attacked, thereby causing a certain degree of material removal. In the example shown, sidewall portion 104S of the isolation structure 105 may suffer from a certain degree of material removal. Consequently, the sidewalls 103S, 104S of the openings 103A, 103B, which may act as an implantation mask during the implantation process 106 (FIG. 1a), may now expose a more or less pronounced portion of the doped regions 131, 132, as indicated by the dashed lines. The increase of at least the opening 103A does have an influence on the finally obtained characteristics of the PN junction 102P after the formation of a metal silicide material.
FIG. 1c schematically illustrates the semiconductor device 100 in a further advanced manufacturing stage in which metal silicide regions 144 are formed in the transistor 140 and metal silicide regions 134 are formed in the doped regions 132, 131 of the substrate diode 130. Due to the preceding material removal at the sidewalls 103S, the metal silicide 134 may extend towards the PN junction 102P and may even result in a short circuit at critical regions 102C, thereby resulting in a complete failure of the substrate diode 130. Even if the metal silicide 134 does not extend across the PN junction 102P in the critical areas 102C, a significant modification of the junction characteristics may result due to the reduced lateral size of the junction region 102P. This may particularly influence the electronic characteristics of sophisticated PN junctions formed in accordance with a process sequence as described above when very sophisticated transistor elements are considered. As a consequence, a more or less modified behavior of the diode characteristic of the substrate diode 130 may result, thereby significantly reducing the reliability of any information obtained on the basis of the substrate diode 130.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.